1. Field of the Invention
The present invention relates to computer systems. More specifically, the present invention relates to techniques for effecting power conservation and management in battery powered personal computers.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art
Power conservation and management is critical for palmtops, laptops and various other battery powered personal computers. The rate of power consumption impacts directly on the length of time the computer may be operated before the batteries must be recharged or replaced. In addition to the inconvenience of changing the batteries, power depletion may occur at a most inopportune time. Accordingly, battery life is a key consideration in the evaluation of competitive products.
Numerous schemes and innovations have been implemented to effect power management. One such scheme involves the automatic powerdown of peripherals (such as a disk drive or a monitor) after a predetermined period of nonuse.
One conventional approach involves the logic implemented through cooperative software and hardware. A separate logic circuit would monitor the line to the peripheral and generate an interrupt to the central processing unit (CPU) which would be effective to disable the device. This approach, however, was difficult to implement. The interrupt had to be protected from or invisible to the user and the user's application software. This approach necessitated considerable additional design and hardware to 1) monitor the peripheral and generate the new interrupt, 2) to recognize the interrupt in the CPU, and 3) to break the flow in the bus from the memory to the processor. In this scheme, thousands of registers and timers are required to monitor the ports and generate the interrupts. The interrupts are always taken. Each time an interrupt is taken a couple hundred instructions are transferred, deciphered and executed. The system is therefore complex and slow.
An alternative scheme involves the assignment of a block of memory for input/output (I/O) operations. The memory is mapped to the I/O ports of the system to which the peripherals are attached. Typically, large adjacent blocks of memory in a high address space are used to which the ports are assigned. The memory provides one bit per port which controls I/O to the port. If the bit is set, I/O is allowed. If not, I/O will not occur but instead will cause an interrupt to occur. Input/output can then be emulated by sending the I/O instruction to memory. (The I/O instruction is a digital word or byte comprised of several bits of digital data. The bits provide the address of the selected I/O port and data to be written to or read from the port.)
In this scheme, power conservation is effected by disabling certain ports due to various factors such as the availability or condition of a peripheral on the machine or a low power state of the battery by way of example. Unfortunately, this method is slow since the interrupt path to the emulation software is typically quite long. Further, I/O managed in this manner also requires that the processor be run in a protected mode to prevent interference from the user's application program. This limits the speed at which the application program can operate.
Thus, there is a need in the art for a technique for managing the input and output operations of a battery powered personal computer to allow high operating speeds with minimal power consumption and minimal additional hardware.